AISC: Approximate Instruction Set Computer

This paper makes the case for a single-ISA heterogeneous computing platform, AISC, where each compute engine (be it a core or an accelerator) supports a different subset of the very same ISA. An ISA subset may not be functionally complete, but the union of the (per compute engine) subsets renders a functionally complete platform-wide single ISA. Tailoring the microarchitecture of each compute engine to the subset of the ISA that it supports can easily reduce hardware complexity. At the same time, the energy efficiency of execution can improve by exploiting algorithmic noise tolerance: by mapping code sequences that can tolerate the incomplete ISA-subsets to the corresponding compute engines. 1 Motivation The ISA specifies semantic and syntactic characteristics of a practically functionally complete set of machine instructions. Modern ISAs are not necessarilymathematically functionally complete, but provide sufficient expressiveness for practical algorithms. For software layers, the ISA defines the underlying machine – as capable as the variety of algorithmic tasks the composition of its building blocks, instructions, can express. For hardware layers, the ISA rather acts as a behavioral design specification for the machine organization. Accordingly, the ISA governs both the functional completeness and complexity of a machine design. This paper makes the case for an alternative, single-ISA heterogeneous computing platform, AISC, which can reduce the ISA complexity, and thereby improve energy efficiency, on a per compute engine (be it a core or an accelerator) basis, without compromising the functional completeness of the overall platform. The distintinctive feature of AISC is that each compute engine supports a different subset of the very same instruction set. Such per compute engine ISA subsets may be disjoint or overlapping. An ISA subset may not be functionally complete, but the union of the (per compute engine) subsets renders platform-wide a functionally complete single ISA. Therefore, software layers perceive AISC as a single-ISA machine. On the other hand, we can tailor the microarchitecture of each compute engine to the subset of the ISA that it supports. The result is less complex, more energy efficient compute engines, without compromising the overall functional completeness of the machine. To be able WAX’18, March 25, 2018 . to exploit this potential, we have to address many questions including • Which subset of the ISA should each compute engine support? • How to guarantee that each sequence of instructions scheduled to execute on a given compute engine only spans the respective subset of the ISA (with potential accuracy loss)? More specifically, how to map instruction sequences to the compute engines? • How to keep the potentially incurred accuracy loss confined? We can approximate the ISA per compute engine along two dimensions: • Horizontal approximation simplifies instructions by reducing complexity (e.g., precision) on a per instruction basis. To be more specific, the subset of the ISA a compute engine implements in this case would selectively contain lower complexity (e.g., lower precision) instructions, by construction. Well-studied precision reduction approaches [2, 5, 6, 8, 10– 12, 14, 16, 17] are directly applicable in this context. Reducing the operand width often enables simplification in the corresponding arithmetic operation, in addition to a more efficient utilization of the available communication bandwidth for data (i.e., operand) transfer. • Vertical approximation eliminates complex and less frequently used instructions. The combination of the two dimensions, Vertical+Horizontal, is also possible: In this case, the compute engine concerned would be able to approximately emulate complex and less frequently used instructions (that its ISA subset does not contain) by a sequence of simpler instructions. Along both dimensions, AISC trades computation accuracy for the complexity (and thereby, energy efficiency) on a per compute engine basis. The compiler and the runtime scheduler have to carefully choose compute engines in scheduling instructions to keep any potential accuracy loss below acceptable thresholds. At the same time, as the entire platform still supports the full-fledged ISA, instruction sequences not prone to approximation can still run at full accuracy. AISC can also be regarded as an aggressive variant of architectural core salvaging [9] or ultra-reduced instruction set coprocessors [15], where actual hardware faults impair a compute engine’s capability to implement a subset of its ISA (and all compute engines support the same ISA by construction). Both of these studies detail how to achieve full-fledged functional completeness under the hardware-fault-induced loss of support for a subset of instructions. AISC, on the 1 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 WAX’18, March 25, 2018 Alexandra Ferrerón1, Jesús Alastruey-Benedé1, Darío Suárez-Gracia1, Ulya R. Karpuzcu2 1Universidad de Zaragoza, Spain 2University of Minnesota, Twin Cities